Improving reliability of weak PUFs via circuit techniques to enhance mismatch

Abstract

In recent years, SRAM-based and other Weak PUFs have found applications in tamper sensitive key storage and ID generation. SRAM-based PUFs, for example, rely on intrinsic process variations to enable repeatable and unique start-up behavior of their outputs. However, noise in the system can compromise repeatability of SRAM start-up behavior. To obviate this problem, a number of solutions such as fuzzy extraction and error correcting codes have been proposed to generate a stable key from PUF cells. However, these methods require a large number of initial PUF bits. In this work, we discuss circuit techniques that create new Weak PUFs by modifying the cross-coupled elements of a traditional storage cell to amplify the impact of process variations and create a higher degree of mismatch. With increased mismatch, the intrinsic error rates of the new PUF cells decrease, thereby reducing the number of PUF cells and amount of auxiliary circuitry needed for fuzzy extraction or ECC. Our results show that the new designs give 4x to 9x reduction in error rates compared to a standard cross-coupled inverter design. We also highlight the area savings that can be achieved in hardware implementations of ECC systems due to improving the inherent reliability of the PUF cells.