Modeling and simulation of 2D-BinDCT based lifting scheme and its integration in a dynamically reconfigurable SOC

Abstract

The Discrete Cosine Transform (DCT) is the most widely used transform for image compression. The DCT approximation or the Binary Discrete Transform (BinDCT) [1] has shown to be a promising alternative to the DCT for its implementation simplicity, close performance and compatibility to the DCT. In this paper, we aim to present efficient VLSI architectures with a low BinDCT complexity implementation. We explore the design of a hardware BinDCT accelerator, the simulation and implementation of the different proposed architectures for a virtex6 FPGA device and its integration in a dynamically reconfigurable SOC. An IP interface was adopted to be able to integrate the proposed hardware accelerator in a SOC. The dynamic partial reconfiguration technique was applied to toggle between the original DCT and BinDCT versions depending on the application requirement. Complete hardware cores, which can be integrated directly in a SOC, was elaborated in order to accelerate the DCT or the BinDCT transform calculation.