{"title":"A high throughput and memory efficient EBCOT architecture for JPEG2000 in digital camera applications","authors":"Yeong-Kang Lai, Lien-Fei Chen, Tai-Lun Huang","doi":"10.1109/ICCE.2005.1429911","DOIUrl":null,"url":null,"abstract":"A high throughput and memory efficient EBCOT (embedded block coding with optimised truncation) architecture for JPEG2000 in a digital camera system is proposed. According to the proposed memory efficient algorithm, three coding state variables (/spl gamma//sub p/[n], /spl sigma//sub p/[n], and /spl pi//sub p/[n]) can be calculated on the fly to eliminate the memory requirement for these three variable. Moreover, three coding passes and four samples within the stripe-column are also performed concurrently by the proposed stripe-column-based pass-parallel operations. Experimental results show that the proposed architecture has 4 times greater throughput than other architectures, and the memory size of the proposed architecture is smaller than other existing architectures.","PeriodicalId":101716,"journal":{"name":"2005 Digest of Technical Papers. International Conference on Consumer Electronics, 2005. ICCE.","volume":"39 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2005 Digest of Technical Papers. International Conference on Consumer Electronics, 2005. ICCE.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCE.2005.1429911","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
A high throughput and memory efficient EBCOT (embedded block coding with optimised truncation) architecture for JPEG2000 in a digital camera system is proposed. According to the proposed memory efficient algorithm, three coding state variables (/spl gamma//sub p/[n], /spl sigma//sub p/[n], and /spl pi//sub p/[n]) can be calculated on the fly to eliminate the memory requirement for these three variable. Moreover, three coding passes and four samples within the stripe-column are also performed concurrently by the proposed stripe-column-based pass-parallel operations. Experimental results show that the proposed architecture has 4 times greater throughput than other architectures, and the memory size of the proposed architecture is smaller than other existing architectures.