Tolerance of delay faults

Abstract

Defect tolerance is traditionally concerned with maintaining system function in the face of spot defects that cause catastrophic circuit faults, such as shorts and opens. This paper describes the problem of spot defects that cause delay faults, and how they can be modeled and characterized in an IC fabrication line. A procedure for simulating the occurrence of such delay faults in a design is described, and results for a number of examples are given. Some techniques for tolerance of delay faults at the architectural and algorithmic level are described.<>