A 60-GHz 90-nm CMOS cascode amplifier with interstage matching

B. Heydari, P. Reynaert, E. Adabi, M. Bohsali, B. Afshar, M. A. Arbabian, A. Niknejad
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引用次数: 26

Abstract

The design of a 60 GHz cascode amplifier in a 90 nm technology is described. The amplifier uses an interstage matching to increase the gain and to provide a better power match between the common-source and the common-gate transistor of the cascode device. Both the common-source and the common-gate transistor make use of an optimized round-table layout, which minimizes all terminal resistances and thus improves the mm-wave performance of the nMOS transistors. A record fmax of 300 GHz is achieved for a 40 mum round-table nMOS in 90 nm CMOS. The cascode amplifier achieves a gain of 7.5 dB at 60 GHz with a DC power consumption of only 6.7 mW. When compared to a shared-junction cascode amplifier or a two-stage common-source cascade amplifier, the presented cascode amplifier is favorable in terms of power gain and DC power consumption
具有级间匹配的60 ghz 90 nm CMOS级联码放大器
介绍了一种采用90nm工艺的60ghz级联码放大器的设计。放大器使用级间匹配来增加增益,并在级联码器件的共源和共栅晶体管之间提供更好的功率匹配。共源晶体管和共栅极晶体管都采用了优化的圆桌布局,使所有终端电阻最小化,从而提高了nMOS晶体管的毫米波性能。在90纳米CMOS中实现了40 μ m圆桌nMOS最大300 GHz的记录。级联放大器在60 GHz时的增益为7.5 dB,直流功耗仅为6.7 mW。与共享结级联放大器或两级共源级联放大器相比,本文提出的级联放大器在功率增益和直流功耗方面具有优势
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