Input sensitive high-level power analysis

2001 IEEE Workshop on Signal Processing Systems. SiPS 2001. Design and Implementation (Cat. No.01TH8578) Pub Date : 2001-09-26 DOI:10.1109/SIPS.2001.957341

J. Hezavei, N. Vijaykrishnan, M. J. Irwin, M. Kandemir, D. Duarte

引用次数: 4

Abstract

An input sensitive table based power estimation technique is proposed. The proposed technique has been applied to different circuits and validated using circuit-level simulation for 0.25 /spl mu/m, 2.5 V CMOS technology. It is observed that the proposed scheme achieves an average error margin of 3.2% as compared to HSPICE, while running 27 times faster.

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输入灵敏的高级功率分析

提出了一种基于输入敏感表的功率估计技术。该技术已应用于不同的电路中，并通过0.25 /spl mu/m, 2.5 V CMOS技术的电路级仿真进行了验证。与HSPICE相比，该方案的平均误差为3.2%，运行速度提高了27倍。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2001 IEEE Workshop on Signal Processing Systems. SiPS 2001. Design and Implementation (Cat. No.01TH8578)

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