A low power and highly reliable 400Mbps mobile DDR SDRAM with on-chip distributed ECC

Abstract

512 Mb Mobile SDRAM with on-chip error-correction code (ECC), which supports either single or double data rate and operates on a 1.8 V power supply, is developed. The ECC circuit is optimized with respect to the increase in the chip area and the access-time penalty. The ratio of ECC area increase compared with the conventional mobile DRAM is 15%, and the fast comparing circuits of built-in Hamming code technique check 12 cell data simultaneously and satisfy the specification of 400Mbps DDR SDRAM. The self refresh period at standby state shows about 6 times increase reducing the self refresh current to be less than 100uA at 85degC. The newly adopted DCCS in the ECC, which is resistant from the clustered failures, and the concurrent row redundancy produce a synergistic fault-tolerance effect. The reliability could be 106 times higher by the ECC than that of the conventional DRAM.