{"title":"The effect of cluster packing and node duplication control in delay driven clustering","authors":"M. E. Dehkordi, S. Brown","doi":"10.1109/FPT.2002.1188686","DOIUrl":null,"url":null,"abstract":"Although delay driven clustering algorithms can optimize circuit delay, they usually result in huge area increase. We present a node duplication control strategy along with a simple packing algorithm that greatly reduce the area penalty with a very small degradation in performance. We use the Quartus Design System from Altera to test our algorithm for a set of MCNC benchmark circuits. The results show that while a 14.5% average delay decrease can be achieved with an average area increase of 240.8%, the algorithm reduces the average area penalty to 27.4% with an average delay decrease of 13.8%. Also the number of clusters and the fitting time reported by Quartus are reduced by more than 91% and 60%, respectively.","PeriodicalId":355740,"journal":{"name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","volume":"11 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/FPT.2002.1188686","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 12
Abstract
Although delay driven clustering algorithms can optimize circuit delay, they usually result in huge area increase. We present a node duplication control strategy along with a simple packing algorithm that greatly reduce the area penalty with a very small degradation in performance. We use the Quartus Design System from Altera to test our algorithm for a set of MCNC benchmark circuits. The results show that while a 14.5% average delay decrease can be achieved with an average area increase of 240.8%, the algorithm reduces the average area penalty to 27.4% with an average delay decrease of 13.8%. Also the number of clusters and the fitting time reported by Quartus are reduced by more than 91% and 60%, respectively.