A 1.5 V circuit technology for 64 Mb DRAMs

Digest of Technical Papers., 1990 Symposium on VLSI Circuits Pub Date : 1990-06-07 DOI:10.1109/VLSIC.1990.111076

Y. Nakagome, Y. Kawamoto, H. Tanaka, K. Takeuchi, E. Kume, Y. Watanabe, T. Kaga, F. Murai, R. Izawa, D. Hisamoto, T. Kisu, T. Nishida, E. Takeda, K. Itoh

引用次数: 32

Abstract

A low-voltage circuit technology for 1.5-V, 64-Mb DRAMs designed to achieve a reasonable speed performance projected from existing trends is described. The DRAM has been deigned using novel low-voltage circuits. An RAS access time of 50 ns has been obtained with power dissipation as low as 44 mW. These results show that a low-voltage battery-operated DRAM is a promising target for the future

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一种用于64mb dram的1.5 V电路技术

描述了一种用于1.5 v, 64mb dram的低压电路技术，旨在实现从现有趋势预测的合理速度性能。该DRAM采用新颖的低压电路设计。获得了50 ns的RAS接入时间，功耗低至44 mW。这些结果表明，低压电池驱动的DRAM是未来有希望的目标

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Digest of Technical Papers., 1990 Symposium on VLSI Circuits

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