A simple countermeasure to mitigate buffer overflow attack using minimalistic hardware-integrated software simulation for FPGA

Abstract

Buffer overflow attack in FPGAs is a persisting problem in the industry and various solutions to mitigate these vulnerabilities are continuously being addressed by manufacturers. A simple and effective mitigation method is proposed and simulated in Vivado using Verilog codes. Checking of bounds of the buffer memory, accompanied by using minimalistic number of logic gates as an encryption method, was simulated and demonstrated to successfully function as a strong countermeasure to this vulnerability.