A light-weight implementation of latch-based true random number generator

Abstract

A TRNG (True Random Number Generator) is an important component for security in mobile computing and IoT. This paper presents an light-weight FPGA implementation of a previously proposed latch-based TRNG, while keeping the quality of generated random numbers. By accumulating the generated random numbers fifteen times with an XOR operation for each output word, the proposed TRNG with 16 latches passed the NIST SP 800-22 test suite, whereas the original TRNG required 248 latches. An important finding of this work is that the quality of random sequence is greatly improved by XOR-ing temporally interleaved series of bits.