A quadruple-sampling second-order delta-sigma modulator

Chien-Hung Kuo, W. Tseng
{"title":"A quadruple-sampling second-order delta-sigma modulator","authors":"Chien-Hung Kuo, W. Tseng","doi":"10.1109/GCCE.2016.7800473","DOIUrl":null,"url":null,"abstract":"In this paper, a 1.8-V 3-bit quadruple-sampling delta-sigma modulator for audio application is presented. To performance high-resolution and low-cost modulator, a single opamp is used to complete the integration with four phases. Since the phase difference between any two succeeding clocks is 90 degrees, the sampling rate will be four times of clock frequency. The effective integration time can also be increased, and thus relaxing the requirements of opamp. From the simulation results, the proposed modulator achieves a peak SNDR of 104.5 dB for 20-kHz signal bandwidth under 1.8-V supply voltage and 2.56 MHz clock rate.","PeriodicalId":416104,"journal":{"name":"2016 IEEE 5th Global Conference on Consumer Electronics","volume":"126 4 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE 5th Global Conference on Consumer Electronics","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/GCCE.2016.7800473","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
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Abstract

In this paper, a 1.8-V 3-bit quadruple-sampling delta-sigma modulator for audio application is presented. To performance high-resolution and low-cost modulator, a single opamp is used to complete the integration with four phases. Since the phase difference between any two succeeding clocks is 90 degrees, the sampling rate will be four times of clock frequency. The effective integration time can also be increased, and thus relaxing the requirements of opamp. From the simulation results, the proposed modulator achieves a peak SNDR of 104.5 dB for 20-kHz signal bandwidth under 1.8-V supply voltage and 2.56 MHz clock rate.
四倍采样二阶δ - σ调制器
本文设计了一种1.8 v 3位四倍采样的音频δ - σ调制器。为了实现高分辨率和低成本的调制器,采用单运放完成四相集成。由于任意两个后续时钟之间的相位差为90度,因此采样率将是时钟频率的四倍。还可以增加有效集成时间,从而放宽对opamp的要求。仿真结果表明,在1.8 v电源电压和2.56 MHz时钟速率下,该调制器在20 khz信号带宽下的峰值SNDR为104.5 dB。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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