Low power techniques and design tradeoffs in adaptive FIR filtering for PRML read channels

K. Muhammad, R. Staszewski, P. Balsara
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引用次数: 1

Abstract

In this paper, we describe area and power reduction techniques for a low-latency adaptive finite-impulse response filter for magnetic recording read channel applications. Various techniques are used to reduce area and power dissipation while speed remains as the main performance criterion for the target application. A parallel transposed direct form architecture operates on real-time input data samples and employs a fast, low-area multiplier based on selection of radix-8 pre-multiplied coefficients in conjunction with one-hot encoded bus leading to a very compact layout and reduced power dissipation. Area, speed and power comparisons with other low-power implementation options are also shown. The proposed filter has been fabricated using a 0.18 /spl mu/m L-effective CMOS technology and operates at 550 MSamples/s.
PRML读通道自适应FIR滤波的低功耗技术和设计权衡
在本文中,我们描述了用于磁记录读通道应用的低延迟自适应有限脉冲响应滤波器的面积和功耗降低技术。采用各种技术来减少面积和功耗,而速度仍然是目标应用的主要性能标准。并行转置直接形式架构在实时输入数据样本上运行,并采用基于基数8预乘系数选择的快速低面积乘法器,结合单热编码总线,导致非常紧凑的布局和降低功耗。还显示了与其他低功耗实现选项的面积、速度和功耗比较。所提出的滤波器采用0.18 /spl mu/m L-effective CMOS技术制造,工作速度为550 MSamples/s。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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