Synthesis of threshold logic gates to nanoelectronics

Abstract

In this paper, a novel method to identify threshold logic functions (TLF) is proposed. Threshold logic is a promising alternative to conventional Boolean logic that has been recently revisited due to the suitability to emerging technologies, such as QCA, RTD, SET, TPL and spintronics. Identification and synthesis of TLF are fundamental tasks for the development of circuit design flow based on such logic style. The proposed method exploits both the order of Chow parameters and the system of inequalities, extracted from a function, to assign optimal variable weights and optimal threshold value. It is the first heuristic algorithm that does not uses integer linear programming (ILP) able to identify all threshold functions with up to five variables. Moreover, it also identifies more functions than other related heuristic methods when the number of variables is higher than five. The proposed algorithm is scalable, since the average execution time is less than 1 ms per function. Furthermore, the method always assigns the minimum weights, resulting in circuits with minimum area.