A Compact 58-65 GHz 6-bit Phase Shifter with 0.7deg/0.35dB RMS Phase/Gain Error in 40nm CMOS Technology

Abstract

This paper presents a 58-65GHz 6-bit active vector synthesis phase shifter (PS) in a 40nm CMOS. To generate I/Q signals, a compact differential capacitor-free quadrature generator circuit (QGC) based on folded transformer is proposed. Two additional transformer-based series peaking are placed between the second-stage amplifier and the digital-to-analog converter (DAC) to obtain wider bandwidth. The post-layout simulation results show that the proposed 6-bit PS achieves a 3-dB band-width of 58 ~ 65GHz. The simulated root-mean-square (RMS) phase error is 0.7° ~ 2.1° and the RMS gain error is 0.35 ~ 0.5dB within the 3-dB bandwidth. The core area of the PS is only $240\text{um}\times 570\text{um}$.