{"title":"The star multiplier","authors":"E. de Angel, A. Chowdhury, E. Swartzlander","doi":"10.1109/ACSSC.1995.540619","DOIUrl":null,"url":null,"abstract":"This paper presents the architecture of a new high speed parallel multiplier. A novel architecture based on two ring structures and the modified-Booth (1951) algorithm achieve high speed multiplications with a significant reduction in hardware. The 32 by 32 bit star multiplier has been designed in a 0.6 /spl mu/m CMOS technology and presents a multiplication time of 17.5 ns.","PeriodicalId":171264,"journal":{"name":"Conference Record of The Twenty-Ninth Asilomar Conference on Signals, Systems and Computers","volume":"46 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Conference Record of The Twenty-Ninth Asilomar Conference on Signals, Systems and Computers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ACSSC.1995.540619","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This paper presents the architecture of a new high speed parallel multiplier. A novel architecture based on two ring structures and the modified-Booth (1951) algorithm achieve high speed multiplications with a significant reduction in hardware. The 32 by 32 bit star multiplier has been designed in a 0.6 /spl mu/m CMOS technology and presents a multiplication time of 17.5 ns.