Lower-part Stochastic Unipolar Adder to Improve Computation Accuracy

Abstract

Stochastic computing is one of approximate computing, which provides lower power consumption through simpler designs with a tolerable error. However, stochastic computing has a fundamental limitation in bit width. The larger the bit size, the longer the computation time. Besides, the error rate also increases as the bit size increases. In this paper, we propose a new stochastic adder, in which stochastic computing is only applied in the lower bits to reduce overall errors in large bit addition. Simulation shows that the proposed design can achieve up to 17x average error reduction compared with the conventional design when a half of the bit is computed stochastically.