FPGA-based architecture of a DS-UWB Channel Estimator and RAKE Receiver employing a hybrid selection scheme

C. Thomos, G. Kalivas
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引用次数: 7

Abstract

A low-complexity architecture of a RAKE Receiver subsystem for a Direct Sequence Ultra-Wideband (DS-UWB) is presented, followed by FPGA implementation and system performance results. The proposed subsystem is composed of a Channel Estimator (CE) and a novel hybrid Partial/Selective (HPS) maximal ratio combining (MRC) RAKE Receiver (RR), which combines the benefits of both partial and selective RAKE receiver algorithms. The implementation of the HPS component is based on a parallel selection structure that picks the strongest multipath rays of the channel impulse response. Our work is focused on a highly parallel, modular design based on FPGA technology and optimized for high performance. The obtained results demonstrate the tradeoff between energy capture, performance and receiver complexity.
基于fpga的DS-UWB信道估计器和采用混合选择方案的RAKE接收机结构
提出了一种用于直接序列超宽带(DS-UWB)的低复杂度RAKE接收子系统架构,并给出了FPGA实现和系统性能测试结果。该子系统由信道估计器(CE)和一种新型的混合部分/选择性(HPS)最大比值组合(MRC) RAKE接收机(RR)组成,该接收机结合了部分和选择性RAKE接收机算法的优点。HPS组件的实现基于一种选择通道脉冲响应中最强多径射线的并行选择结构。我们的工作重点是基于FPGA技术的高度并行模块化设计,并针对高性能进行了优化。获得的结果证明了能量捕获,性能和接收器复杂性之间的权衡。
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