{"title":"FPGA-based architecture of a DS-UWB Channel Estimator and RAKE Receiver employing a hybrid selection scheme","authors":"C. Thomos, G. Kalivas","doi":"10.1109/ICTEL.2010.5478836","DOIUrl":null,"url":null,"abstract":"A low-complexity architecture of a RAKE Receiver subsystem for a Direct Sequence Ultra-Wideband (DS-UWB) is presented, followed by FPGA implementation and system performance results. The proposed subsystem is composed of a Channel Estimator (CE) and a novel hybrid Partial/Selective (HPS) maximal ratio combining (MRC) RAKE Receiver (RR), which combines the benefits of both partial and selective RAKE receiver algorithms. The implementation of the HPS component is based on a parallel selection structure that picks the strongest multipath rays of the channel impulse response. Our work is focused on a highly parallel, modular design based on FPGA technology and optimized for high performance. The obtained results demonstrate the tradeoff between energy capture, performance and receiver complexity.","PeriodicalId":208094,"journal":{"name":"2010 17th International Conference on Telecommunications","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 17th International Conference on Telecommunications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICTEL.2010.5478836","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7
Abstract
A low-complexity architecture of a RAKE Receiver subsystem for a Direct Sequence Ultra-Wideband (DS-UWB) is presented, followed by FPGA implementation and system performance results. The proposed subsystem is composed of a Channel Estimator (CE) and a novel hybrid Partial/Selective (HPS) maximal ratio combining (MRC) RAKE Receiver (RR), which combines the benefits of both partial and selective RAKE receiver algorithms. The implementation of the HPS component is based on a parallel selection structure that picks the strongest multipath rays of the channel impulse response. Our work is focused on a highly parallel, modular design based on FPGA technology and optimized for high performance. The obtained results demonstrate the tradeoff between energy capture, performance and receiver complexity.