{"title":"An on-line software-based self-test framework for microprocessor cores","authors":"A. Benso, A. Bosio, P. Prinetto, A. Savino","doi":"10.1109/DTIS.2006.1708654","DOIUrl":null,"url":null,"abstract":"Software-based self-test (SBST) in embedded microprocessor cores testing allows lowering test costs without loosing fault detection capabilities. Particularly in critical environments, SBST is executed during the system operating life in order to guarantee its availability and quality of service. If the test routines can be executed online but not-concurrently, then both the hardware and software overheads are negligible. This paper presents results and issues faced during the development of SBST approach targeting a Motorola PowerPC 603 core. The test, constrained by tight timing and coverage requirements, required the development of a general framework, easily reusable on other microprocessor cores","PeriodicalId":399250,"journal":{"name":"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.","volume":"45 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DTIS.2006.1708654","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 8
Abstract
Software-based self-test (SBST) in embedded microprocessor cores testing allows lowering test costs without loosing fault detection capabilities. Particularly in critical environments, SBST is executed during the system operating life in order to guarantee its availability and quality of service. If the test routines can be executed online but not-concurrently, then both the hardware and software overheads are negligible. This paper presents results and issues faced during the development of SBST approach targeting a Motorola PowerPC 603 core. The test, constrained by tight timing and coverage requirements, required the development of a general framework, easily reusable on other microprocessor cores