Optimization of PCB PDN design using enhanced VRM model

Abstract

Decoupling for power rails that demand large current, such as FPGA core, is difficult. The capacitors required for derived solution requires excessive board area for placement and raise system cost significantly. Switcher with high loop Band Width helps reducing the decoupling needs with all the design improvements. In this paper, we proposed a 3-stage behavioral model for switcher to help PCB designer optimize PCB decoupling design. The paper also covers some issues related to switcher application, such as layout optimization for best noise performance.