High Speed Multiplier using Embedded Approximate 4-2 Compressor for Image Multiplication

Abstract

Multiplication is the most widely used operation in a variety of applications such as digital filters and neural networks. In certain applications (image processing), precise computation is not required and, even low-accuracy computing can yield meaningful results. Since approximate computing is less complex and consumes less resources, it can be used in image processing and multimedia applications. Regular adders have a longer critical delay than compressor adders, making them suitable for use in multiplier architectures. Compressors can be employed in multiplication operations to reduce number of partial products, delay and power dissipation. We presented a 8×8 Dadda multiplier with an approximated 4:2 compressor in this research. On a pixel-by-pixel basis, this multiplier is used to multiply two images.