A 4-GHz low-power TDC-based all digital PLL having 9.6mW and 1.2ps rms jitter

Abstract

This paper presents a 4-GHz ADPLL with low-power TDC using two low-rate retimed reference clocks (pCKR, nCKR) to measure the fractional phase error between the reference clock edge and DCO clock edge. The application of the retimed reference clocks enables TDC to avoid metastability of its sampling register as well as alleviate large dynamic power of its delay inverter chain. A mode-decision block is also proposed to generate suitable control signals for accomplishing seamless movement of DCO operation mode. The proposed ADPLL achieves − 95 dBc/Hz in-band phase noise and 1.2ps rms jitter, consuming 9.6mW.