One-neuron circuitry for carry generation in a 4-bit adder

Abstract

It is shown how a parallel carry generator circuit using the sigmoidal (input/output) characteristic of a neuron can be employed in a carry select adder architecture. The circuit performs the carry generation function in parallel with the generation of the summation bits. By examining the input-output pairs of a digital adder it is found that the generation of its output carry is a most basic mapping of a neural network, the mapping of a single neuron. The realization of this mapping by a transistor circuit is described. Performance results derived from SPICE simulations of the proposed circuit, using 1.2- mu m CMOS technology, are also given.<>