An efficient computation of minimal correction subformulas for SAT-based ATPG of digital circuits

Abstract

Lately, research has been focused on the problem of extracting the main unsatisfiable cores from infeasible constraints. The main reasons of infeasibility can be represented by subsets of unsatisfied clauses referred to “Minimal Correction Subsets”. Various developed algorithms for computing MCSes can be used for fault detection technique which is considered a core of SAT-based Automatic Test Pattern Generation (ATPG) on digital VLSI circuits. This paper presents an efficient CPU-GPU algorithm for extracting the complete MCSes that can be optimized on NVIDIA General Purpose Graphics Processing Unit paradigm which is considered one of the most common platforms for GPU parallel computing. Our proposed algorithm is evaluated using a C++ algorithm for generating and reducing a SAT instance of VLSI digital circuits from ISCAS'85, ISCAS'89 and synthetic benchmarks. The proposed algorithm, utilizing our presented parallel SAT-solver, delivers about 1.4x speedup compared to the CUDA@SAT tool.