Dynamic and Reliable Multichannel Interfacing System for FPGAs

Abstract

The focus in this paper is on FPGA-based systems with processors communicating with interchangeable device boards using shared interfaces implementing protocols such as UART, SPI, and I2C. A design is proposed to allow the dynamic interface switching using Dynamic Partial Reconfiguration (DPR) in order to increase performance or reliability during runtime. To this end, a reconfigurable interface block is introduced along with a switching block to connect any interface to different FPGA pins. Furthermore, it is shown how to add redundant interface blocks in order to achieve a pre-determined reliability level. Markov models are used in this analysis. All three protocols were implemented using DE10-Standard FPGA boards.