A Cost and Performance Analytical Model for Large-Scale On-Chip Interconnection Networks

Abstract

As an interconnection topology, two-dimensional mesh is widely used in the design of the network-on-chip (NoC) for integrating dozens of cores on a VLSI chip because of its very simple structure and ease of on-chip implementation. However, as the progress of IC technology, it becomes possible to integrate a large-scale system on a chip that contains more than one thousand processing elements or cores. In such a case, mesh topology will deteriorate performance due to the increase of communication time among cores. This paper investigates topologies and IC layout schemes of mesh, torus, hypercube, and metacube for achieving good cost-performance tradeoffs. We propose an analytical model for evaluating cost-performance ratio by considering NoC's topology and layout. The model is parameterized with node degree, graph diameter, the number of routers, the router complexity, the bandwidth of the connection for the router, the number of processing cores, the total length of links, and the cost ratios of the link section and the router section. This model is helpful for us to find out the optimal topology and layout for NoC with a given network size. It was found that when the network size is small, mesh has a better cost-performance than others; as the network size increases, torus and hypercube outperform mesh; and metacube has the best cost-performance among them.