{"title":"The design of Neural A/D converter using neuron-MOS transistor","authors":"G. Hang, Guofei Wang, Xiaohui Hu","doi":"10.1109/ICNC.2012.6234650","DOIUrl":null,"url":null,"abstract":"A novel circuit realization of two parallel A/D converters based on the Hopfield's neural network is presented. The two neural A/D converters are constructed with comparators and Schmitt triggers, respectively, and they are all designed by using neuron-MOS transistors. The benefit of the proposed circuit realization with neuron-MOS transistors is that the structure of the circuit has been simplified significantly. The proposed circuits can be fabricated by standard CMOS process with a 2-ploy layer. From the HSPICE simulation results using TSMC 0.35μm double-polysilicon CMOS technology, the effectiveness of the proposed approach is validated.","PeriodicalId":404981,"journal":{"name":"2012 8th International Conference on Natural Computation","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 8th International Conference on Natural Computation","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICNC.2012.6234650","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
A novel circuit realization of two parallel A/D converters based on the Hopfield's neural network is presented. The two neural A/D converters are constructed with comparators and Schmitt triggers, respectively, and they are all designed by using neuron-MOS transistors. The benefit of the proposed circuit realization with neuron-MOS transistors is that the structure of the circuit has been simplified significantly. The proposed circuits can be fabricated by standard CMOS process with a 2-ploy layer. From the HSPICE simulation results using TSMC 0.35μm double-polysilicon CMOS technology, the effectiveness of the proposed approach is validated.