Implementation of a high-speed pipelined FFT processor using dadda multipliers to process two independent data streams

Abstract

Present real time applications require high speed fast Fourier transform (FFT) processors to process multiple independent data streams. This paper presents a high speed pipelined FFT processor to process two independent data streams concurrently. This processor takes inputs in normal order and generates outputs also in normal order. In this architecture, two N/2-point multipath delay commutator (MDC) FFT architectures are used to process even and odd samples of two data streams separately. To process bit reversal operations at different stages, the processor uses shift registers whose actual purpose is to delay the samples of data streams. So it does not require additional bit reversal circuits for getting normal output order. To get high computational speed, Dadda multipliers are used in the computation of butterfly processing elements. That multiplier is based on row reduction by compressing columns using less full adders and half adders compared to the conventional multipliers. Thus the Dadda multiplier's speed is more and takes less hardware. Therefore, by using the Dadda multipliers, the proposed FFT architecture has high speed of the computation and requires less hardware.