Design and Implementation of low power 4 × 4/8 × 8 2D-DTT architecture for image and video compression

Abstract

This work proposes low power and high throughput hardware architectures of various sizes 4 4,8 8 forward DTT and inverse DTT(IDTT) of semi parallel, fully parallel and a scalable implementation of DTT is also explored in this work. The proposed architectures are multiplier-free, produce high throughput. The designs are implemented on Field Programmable Gate Array(FPGA) and Application Specific Integrated Circuit(ASIC) platforms at TSMC 180 nm technology. The results show that proposed hardware architectures can support processing of 4K Ultra High Definition(UHD) video sequence at 21.6 fps and 10.2 fps of 8×8 and 4×4 DTT respectively operating at 23.8 MHz. Experimental results are compared with state-of-the-art literature which conclude that the proposed architectures consume lesser amount of resources with less processing clock cycles.