R. Hickling, R. A. Kot, M. Yagi, R. Nagarajan, W. Sha, R. Craig
{"title":"Low power components for 1 Gb/s optical communications: A single-chip 10-channel optical receiver and a clock recovery circuit","authors":"R. Hickling, R. A. Kot, M. Yagi, R. Nagarajan, W. Sha, R. Craig","doi":"10.1109/GAAS.1997.628269","DOIUrl":null,"url":null,"abstract":"A single chip, 10-channel optical transimpedance receiver and a low-power, single channel clock recovery circuit have been designed and characterized. The 10-channel receiver operates from a single 3.3 V or 5 V power supply, is capable of automatic offset correction, and generates ECL or PECL output levels. The clock recovery circuit operates from a single 5 V power supply and is based upon a novel variation on the so-called early-late gate bit synchronizer loop.","PeriodicalId":299287,"journal":{"name":"GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 19th Annual Technical Digest 1997","volume":"37 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 19th Annual Technical Digest 1997","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/GAAS.1997.628269","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
A single chip, 10-channel optical transimpedance receiver and a low-power, single channel clock recovery circuit have been designed and characterized. The 10-channel receiver operates from a single 3.3 V or 5 V power supply, is capable of automatic offset correction, and generates ECL or PECL output levels. The clock recovery circuit operates from a single 5 V power supply and is based upon a novel variation on the so-called early-late gate bit synchronizer loop.