A 60 GHz Power Amplifier in 90nm CMOS Technology

2007 IEEE Custom Integrated Circuits Conference Pub Date : 2007-09-01 DOI:10.1109/CICC.2007.4405843

B. Heydari, M. Bohsali, E. Adabi, A. Niknejad

引用次数: 42

Abstract

A two-stage 60 GHz 90 nm CMOS PA has been designed and fabricated. The amplifier has a measured power gain of 9.8 dB. The input is gain matched while the output is matched to maximize the output power. The measured P-1dB = 6.7 dBm with a corresponding power added efficiency of 20%. This amplifier can be used as a pre-driver or as the main PA for short range wireless communication. The output power can be boosted with on-chip or spatial power combining.

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基于90nm CMOS技术的60ghz功率放大器

设计并制作了一种两级60 GHz 90 nm CMOS PA。该放大器的测量功率增益为9.8 dB。输入是增益匹配，而输出匹配，以最大限度地提高输出功率。测量的P-1dB = 6.7 dBm，相应的功率增加效率为20%。该放大器可以用作前置驱动器，也可以用作短距离无线通信的主扩音器。输出功率可以通过片内或空间功率组合来提高。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2007 IEEE Custom Integrated Circuits Conference

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