Towards a Generic UVM

Abstract

In the modern era of CPU complexity advancements, Processor verification has always been an ever-increasing challenge. The gap between what a verification plan can offer nowadays and the current technology requirements is constantly widened. Despite many efforts on perfecting “Golden-verification-models” during the design phase, and adoption of object-oriented programming into the whole process; many industry experts still consider solo verification test benches as an extreme, time-consuming barricade that leads to a longer time-to-market and a questionable continuity of the current verification process. The Universal Verification Methodology (UVM), came in action as a literal savior to the whole verification community, by offering a merge between System Verilog and SystemC into one environment that is completely standardized, constrained, and reusable, allowing a powerful verification methodology to a wide range of design sizes and types. The main contribution that this project introduces is implementing a generic UVM, in other words, building one verification environment that can be used to accommodate many RTL designs (Soft Processors), having not only different Instruction Set Architectures (ISAs) -of the same categories-, but also different techniques/mechanisms handling the pipeline infrastructures. The proposed generic UVM (GUVM) structure permits the targeted user to attach any soft processor (core) having nearly the same micro-architecture to our test bench, and monitor both: CPU internal behavior and the complete flow of all supported instructions.