{"title":"Multiple-poles multilevel diode-clamped inverter (M2DCI) topology for alternative multilevel converter","authors":"G. H. P. Ooi, A. Maswood, A. Venkataraman","doi":"10.1109/ASSCC.2012.6523318","DOIUrl":null,"url":null,"abstract":"This paper introduces a multiple-poles multilevel diode-clamped inverter (M2DCI) topology. Presented topology is able to synthesis nth-level of output voltage steps with isolated dc voltage source and simple cascaded sub-cell can be easily connected in parallel mode to achieve higher voltage levels. This paper discusses seven-level voltage steps on the output terminal of the inverter. The presented topology provides several merits of low output voltage distortion, low voltage stress and higher voltage levels. The basic structure of seven-level multiple-poles multilevel diode-clamped inverter (7L-M2DCI) topology is to keep the design simple and reduce number of components count as compared with classical seven-level multilevel flying capacitor inverter (7L-MFCI) and seven-level multilevel diode-clamped inverter (7L-MDCI) topologies. Hence, components comparisons of classical MDCI and M2DCI topologies are presented and simple analysis of 7L-M2DCI topology is discussed in this context. To operate effectiveness of 7L-M2DCI topology, a level-shifted pulse width modulation (LS-PWM) technique is presented and simulation results are verified for the operating stages of the proposes 7L-M2DCI converter.","PeriodicalId":341348,"journal":{"name":"2012 10th International Power & Energy Conference (IPEC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"16","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 10th International Power & Energy Conference (IPEC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2012.6523318","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 16
Abstract
This paper introduces a multiple-poles multilevel diode-clamped inverter (M2DCI) topology. Presented topology is able to synthesis nth-level of output voltage steps with isolated dc voltage source and simple cascaded sub-cell can be easily connected in parallel mode to achieve higher voltage levels. This paper discusses seven-level voltage steps on the output terminal of the inverter. The presented topology provides several merits of low output voltage distortion, low voltage stress and higher voltage levels. The basic structure of seven-level multiple-poles multilevel diode-clamped inverter (7L-M2DCI) topology is to keep the design simple and reduce number of components count as compared with classical seven-level multilevel flying capacitor inverter (7L-MFCI) and seven-level multilevel diode-clamped inverter (7L-MDCI) topologies. Hence, components comparisons of classical MDCI and M2DCI topologies are presented and simple analysis of 7L-M2DCI topology is discussed in this context. To operate effectiveness of 7L-M2DCI topology, a level-shifted pulse width modulation (LS-PWM) technique is presented and simulation results are verified for the operating stages of the proposes 7L-M2DCI converter.