Advanced performance features of the 64-bit PA-8000

Abstract

The PA-8000 is Hewlett-Packard's first CPU to implement the new 64-bit PA2.0 architecture. It combines a high clock frequency with a number of advanced microarchitectural features to deliver industry-leading performance on commercial and technical applications while maintaining full compatibility with all previous PA-RISC binaries. Among these advanced features are a fifty-six entry instruction reorder buffer to support out-of-order execution, a branch target address cache, branch history table, support for multiple outstanding cache misses and dual integer load/store, floating point multiply/accumulate, and divide/square root units which allow execution of four instructions per cycle. Together these features will enable the PA-8000 to sustain superscalar operation on a wide variety of workloads.