{"title":"Automated schematic capture and the UCS51 (microcontroller)","authors":"E.M. Aleman","doi":"10.1109/ASIC.1989.123250","DOIUrl":null,"url":null,"abstract":"The author introduces automated schematic capture configuration for the UCS51 embedded microcontroller, which is based on the 80C51 microcontroller, and its five accompanying peripherals. In addition, current automation applications are outlined. The UCS51 design entry tool, a menu-driven automated schematic capture/configuration procedure, is discussed step by step, menu by menu. The discussion includes mapping the peripheral registers into the special function register bus where they may be directly accessed to support the full logical functions of the core's instruction set. 'How to' and sample schematics are shown for each configuration. Future and related applications are also explored.<<ETX>>","PeriodicalId":245997,"journal":{"name":"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,","volume":"66 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASIC.1989.123250","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
The author introduces automated schematic capture configuration for the UCS51 embedded microcontroller, which is based on the 80C51 microcontroller, and its five accompanying peripherals. In addition, current automation applications are outlined. The UCS51 design entry tool, a menu-driven automated schematic capture/configuration procedure, is discussed step by step, menu by menu. The discussion includes mapping the peripheral registers into the special function register bus where they may be directly accessed to support the full logical functions of the core's instruction set. 'How to' and sample schematics are shown for each configuration. Future and related applications are also explored.<>