An Innovative Fault-Tolerant Method for 2-D Mesh-Based Network-on-Chip Routing

Abstract

Fault-tolerant routing algorithms are key concerns in Network-on-Chip (NoC) communication. This paper proposes a high performance fault-tolerant routing algorithm based on Fault-Tolerant-Routing (FTR) as a new solution to decrease delay of the messages over the on-chip interconnection mesh networks. The FTR algorithm is a wormhole-switched routing for 2-D mesh networks and has been used for block faults. This algorithm uses virtual channels to pass faulty regions. We have improved the FTR algorithm to decrease message delays in the network without adding new extra virtual channels which led to an Improved-Fault-Tolerant-Algorithm (i-FTR). Moreover, to simulate FTR and i-FTR algorithms, same network conditions namely network size, message length and number of generated messages has been considered. It can be deduced from results that i-FTR performs better compared to FTR algorithm. Furthermore, results show that the interconnection network of NoC which has been used for i-FTR can deal with higher message rates and can tolerate higher traffic loads.