Error Control to Increase the Yield of Semiconductor RAM's

R. Krishnamoorthy, C. Heegard
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Abstract

A hard defect in a semiconductor random access memory (RAM) is a cell which is "stuck-at" a certain value or is otherwise consistently unreliable. The most commonly used technique to correct hard defects during manufacturing is row/column replacement, wherein redundant rows and columns are added on to each memory array and are used to replace rows and columns which contain defective cells. This method has been applied to memory chips of modest sizes (in the 64 K - 4 M bit range). However, the strategy of replacing an entire row or column because of a single defective cell seems likely to be inefficient as the size of the memory array grows. Our research effort was motivated by a recent paper [l] in which this technique is shown to be asymptotically ineffective: as the size of the memory array grows, regardless of the rate (the amount of redundancy) the probability of obtaining an error-free array approaches zero. We consider implementing an error correcting code (ECC) on the memory array in order to control hard defects. A simple single-errorcorrecting code is used over the rows, each row containing an integral number of codewords. Since each codeword can tolerate up to one defect, this technique allows the array to suffer some defective cells and still exhibit no loss of fidelity. We analyze the yield (the probability that a chip is defect-free) due to this method, using a shortenend Hamming code to illustrate our results. The presence of multiple defective cells in some codewords would cause these codewords to become undecodable, causing the chip to be rejected. In order to further improve the yield, we also consider using redundant rows and columns in conjunction with an ECC to correct undecodable codewords in the memory array. It is to be noted that we are interested in improving the yield of memory chips which suffer from single cell defects. In the case of an entire row or column failing (due to the failure of a row driver or a column decoder) we cannot, of course, do any better than to replace the entire row or column. Algorithms to switch rows and columns are examined, and three separate cases are considered: (1) redundant rows, (2) redundant columns, and (3) redundant rows and columns. Case (1) is easily analyzed. Cases (2) and (3) are much more difficult: it is shown that the problem of finding an optimal algorithm to switch columns (case (2)) is inherently intractable, and we prove that this problem is NP - complete. As a corollary, the problem of simultaneously switching rows and columns is also shown to be NP - complete. Heuristics for cases (2) and (3) are presented, and bounds on the yield due to these techniques are derived. References
提高半导体RAM成品率的误差控制
半导体随机存取存储器(RAM)中的硬缺陷是一个单元“卡在”某个值上或在其他方面始终不可靠。在制造过程中最常用的纠正硬缺陷的技术是行/列替换,其中将冗余的行和列添加到每个存储器阵列中,并用于替换包含有缺陷单元的行和列。该方法已应用于中等尺寸的存储芯片(在64k - 4m位范围内)。然而,由于单个有缺陷的单元而替换整个行或列的策略,随着内存阵列的大小增长,似乎效率很低。我们的研究工作是由最近的一篇论文[1]所激发的,在这篇论文中,这种技术被证明是渐近无效的:随着存储器阵列的大小的增长,无论速率(冗余量)如何,获得无错误阵列的概率接近于零。为了控制硬缺陷,我们考虑在存储器阵列上实现一个纠错码(ECC)。在这些行上使用一个简单的单错误纠错码,每行包含一个整数的码字。由于每个码字最多可以容忍一个缺陷,这种技术允许阵列遭受一些有缺陷的细胞,但仍然不会失去保真度。由于这种方法,我们分析了产量(芯片无缺陷的概率),使用缩短的汉明码来说明我们的结果。在一些码字中存在多个有缺陷的细胞会导致这些码字变得不可解码,导致芯片被拒绝。为了进一步提高产量,我们还考虑将冗余行和列与ECC结合使用,以纠正内存数组中不可解码的码字。值得注意的是,我们感兴趣的是提高单细胞缺陷的存储器芯片的产量。在整个行或列失败的情况下(由于行驱动程序或列解码器的失败),我们当然不能做比替换整个行或列更好的事情。检查了切换行和列的算法,并考虑了三种不同的情况:(1)冗余行,(2)冗余列,(3)冗余行和列。案例(1)很容易分析。用例(2)和(3)要困难得多:我们证明了寻找切换列(用例(2))的最优算法的问题本质上是难以处理的,并且我们证明了这个问题是NP完全的。作为一个推论,同时交换行和列的问题也被证明是NP完全的。给出了情况(2)和(3)的启发式方法,并推导了由于这些技术而产生的产量界限。参考文献
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