A skew tolerant CMOS level-based ATM data-recovery system without PLL topology

Abstract

In high-speed communication systems with multiple inputs from different origins, all data have to be retimed to the clock of the DSP. This paper describes a data-recovery system which allows a 25% tolerance on the absolute position of the edge. The intelligent sample selector with memory-function retrieves the correct data from the multisampled input, even under the circumstances of wander, clock- and data-jitter and propagation phase-shift. The used approach does not require a PLL nor a DLL, since the straightforward mechanism results in the capture of the transmitted data with only the use of the central clock of the DSP. The retiming is done already at the first level-change and further at each following level-change. The good results are proven with measurements on a realisation with standard cells in a standard 0.7 /spl mu/m CMOS technology.