Influence of different layout styles on the performance of the calibration of an on-chip programmable voltage reference

Abstract

This paper presents an on-chip programmable voltage reference circuit whereat the main block, the switchable resistor array, was realized using four different layout styles. These different layouts, which result in different complexity and chip area consumptions, are analyzed regarding the influence on the calibration performance of the voltage reference circuit. Although a slight difference can be measured, there is no clear preference for one of the four layout versions. In contrast to the much smaller chip area of the more or less lumped approach (lay3) the distributed approach (lay0) shows only slight advantages in circuit performance.