Distributed logic simulation algorithm using preemption of inconsistent events

Abstract

Parallel processing offers a viable alternative to improve the enormous execution time of logic simulation of large VLSI designs. Various parallel logic simulation schemes have been proposed in recent years on achieving speedup using conservative and optimistic asynchronous algorithms. In this paper, we have proposed a new algorithm, capable of preempting inconsistent events and also reducing the number of messages sent among processors, resulting in faster simulation. Usage of prediction time, in both sequential and combinational circuits, gives capability of preempting inconsistent events and thereby supporting the rise/fall delay model for conservative event driven simulation. Implementation of the proposed algorithm has been carried out in a network of IBM RISC 6000/300 system workstations. Results of the proposed algorithm is compared with the null message based CM algorithm, and it was found that proposed algorithm more efficiently compared to the CM algorithm in case of sequential circuits and works as good as CM algorithm in combinational circuits.