Validation Testing of IEC 61850 Process Bus Architecture in a Typical Digital Substation

Abstract

This paper examines the challenges posed to protection devices in IEC 61850 process bus systems, and the impacts that the process bus architecture has on the reliability of protection. A hardware in the loop setup is used with merging units, communication networks, and test sets to establish a smallscale actual substation. Next, a software-based sampled values generator was built to examine the impacts of extreme delay, missing and invalid samples on a real protection IED. Solutions to minimize the impact of delayed, missing, and invalid samples are then proposed and evaluated for their impact on the protection device. This paper highlights the common issues with process bus systems and the effectiveness of some solutions to these challenges from the perspective of protection.