A Monolithic 2.44 GHz Transceiver Frontend

Abstract

The design, fabrication and prototype evaluation of a single chip transceiver frontend for the 2.44 GHz-frequency band is presented. The chip architecture, circuit design and the measured, results are described. The transmitter section of the IC comprises an interface to CMOS logic, a BPSK modulator providing the high carrier suppression needed for direct spread spectrum modulation, and an RF driver amplifier. The receive section is aconventional downcotiverter with an LNA stage, amixerand a three stage IF preamplifier (frequency range 50 to 500 MHz) with gain control. In addition, the chip includes a local oscillator chain to feed both TX and RX mixers (1.2 GHz oscillator, prescaler for PLL support and frequency doubler). Chip size. and power consumption is 3 mm2 and 400 mW repectively. The prototypes have been produced with a commercial GaAs-E/D foundry process and may find application in WLAN or future low cost PCS terminals.