{"title":"A low power cross-coupled charge pump with charge recycling scheme","authors":"Hye-Won Hwang, J. Chun, K. Kwon","doi":"10.1109/ICSCS.2009.5412265","DOIUrl":null,"url":null,"abstract":"A low power charge pump that recycles the wasted charges is described. CMOS switched Dickson charge pump cannot accommodate charge recycling since charges are leaking from the boosted supply (VPP) back to the external supply (VDD) during the recycling period. Given power constraints, the proposed 2-stage cross-coupled pump with leak-back current suppression can provide the current 5 times higher than that of the conventional cross-coupled pump at VPP of 5V. Its maximum achievable VPP is also 1.6 times higher. The test chip is under fabrication using 0.18um CMOS technology.","PeriodicalId":126072,"journal":{"name":"2009 3rd International Conference on Signals, Circuits and Systems (SCS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"14","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 3rd International Conference on Signals, Circuits and Systems (SCS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICSCS.2009.5412265","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 14
Abstract
A low power charge pump that recycles the wasted charges is described. CMOS switched Dickson charge pump cannot accommodate charge recycling since charges are leaking from the boosted supply (VPP) back to the external supply (VDD) during the recycling period. Given power constraints, the proposed 2-stage cross-coupled pump with leak-back current suppression can provide the current 5 times higher than that of the conventional cross-coupled pump at VPP of 5V. Its maximum achievable VPP is also 1.6 times higher. The test chip is under fabrication using 0.18um CMOS technology.