A design tool for the specification and the simulation of array processors architectures application to image processing: the extraction of regions of interests

Abstract

This paper deals with a CAD tool dedicated to the design and the simulation of specific array processor architectures. These architectures are described into a specific notation which includes major characteristics of the VHDL syntax. This language provides a very concise and legible means to specify array processors. A preprocessor generates full standard VHDL code describing the behavior of the designed architecture. An original application to image processing is given: the design of a specific architecture for the extraction of regions of interests.