Observation Point Insertion Using Deep Learning

Bonita Bhaskaran, Sanmitra Banerjee, Kaushik Narayanun, Shao-Chun Hung, Seyed Nima Mozaffari Mojaveri, Mengyun Liu, Gang Chen, Tung-Che Liang
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Abstract

Silent Data Corruption (SDC) is one of the critical problems in the field of testing, where errors or corruption do not manifest externally. As a result, there is increased focus on improving the outgoing quality of dies by striving for better correlation between structural and functional patterns to achieve a low DPPM. This is very important for NVIDIA's chips due to the various markets we target; for example, automotive and data center markets have stringent in-field testing requirements. One aspect of these efforts is to also target better testability while incurring lower test cost. Since structural testing is faster than functional tests, it is important to make these structural test patterns as effective as possible and free of test escapes. However, with the rising cell count in today's digital circuits, it is becoming increasingly difficult to sensitize faults and propagate the fault effects to scan-flops or primary outputs. Hence, methods to insert observation points to facilitate the detection of hard-to-detect (HtD) faults are being increasingly explored. In this work, we propose an Observation Point Insertion (OPI) scheme using deep learning with the motivation of achieving - 1) better quality test points than commercial EDA tools leading to a potential lower pattern count 2) faster turnaround time to generate the test points. In order to achieve better pattern compaction than commercial EDA tools, we employ Graph Convolutional Networks (GCNs) to learn the topology of logic circuits along with the features that influence its testability. The graph structures are subsequently used to train two GCN-type deep learning models - the first model predicts signal probabilities at different nets and the second model uses these signal probabilities along with other features to predict the reduction in test-pattern count when OPs are inserted at different locations in the design. The features we consider include structural features like gate type, gate logic, reconvergent-fanouts and testability features like SCOAP. Our simulation results indicate that the proposed machine learning models can predict the probabilistic testability metrics with reasonable accuracy and can identify observation points that reduce pattern count.
使用深度学习的观测点插入
静默数据损坏(SDC)是测试领域的关键问题之一,其中错误或损坏不会在外部显示。因此,通过努力实现结构和功能模式之间更好的相关性来实现低DPPM,从而增加了对提高模具出厂质量的关注。这对NVIDIA的芯片非常重要,因为我们的目标市场多种多样;例如,汽车和数据中心市场有严格的现场测试要求。这些努力的一个方面是在降低测试成本的同时,还以更好的可测试性为目标。由于结构测试比功能测试快,因此使这些结构测试模式尽可能有效并避免测试转义是很重要的。然而,随着当今数字电路中单元数的增加,将故障敏感化并将故障影响传播到扫描触发器或主输出变得越来越困难。因此,人们越来越多地探索插入观测点以方便检测难以检测(HtD)故障的方法。在这项工作中,我们提出了一种使用深度学习的观察点插入(OPI)方案,其动机是实现- 1)比商业EDA工具更好的质量测试点,导致潜在的更低的模式计数2)更快的周转时间来生成测试点。为了实现比商业EDA工具更好的模式压缩,我们使用图卷积网络(GCNs)来学习逻辑电路的拓扑结构以及影响其可测试性的特征。图结构随后用于训练两个gcn类型的深度学习模型——第一个模型预测不同网络上的信号概率,第二个模型使用这些信号概率以及其他特征来预测在设计的不同位置插入op时测试模式计数的减少。我们考虑的特征包括结构特征,如门类型、门逻辑、再收敛扇出和可测试性特征,如SCOAP。仿真结果表明,所提出的机器学习模型能够以合理的精度预测概率可测试性度量,并能够识别减少模式计数的观察点。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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