20 Gb/s Monolithic Integrated Clock Recovery and Data Decision

Abstract

An IC for 20 Gb/s clock recovery and data decision was realised using 0.3 ¿m gate-length QW-HEMTs. A narrow-band regenerative frequency divider with on-chip resonator filters is used for the clock recovery. The parallel processing concept is accepted for the data decision. The complex IC was tested on wafer using 5 and 10-Gb/s input data. The desired 10-GHz clock signal and regenerated data signals have been obtained. The 2×2 mm2 IC has a power consumption of about 0.5 W at ¿3 volt supply voltage.