PCB Layout Parasitic Parameter Verification Using Multi-Frequency Analysis

Abstract

Gallium Nitride High Electron Mobility Transistor (GaN HEMT) is one of the most promising candidates for next generation power devices due to its electrical characteristics. However, the weakness of GaN HEMT is its fragile gate that does not tolerate voltage noise well. Researchers and companies have made great efforts on evaluating parasitic inductance from PCB layout at frequency of several hundred kHz or above. In this paper, a new procedure for evaluating parasitic parameter is introduced. It consists of two parts, the first part is a condensed process that use software to extract parasitic while saving great efforts on environment setup. The second part is a multi-frequency analysis method that superimpose several simulation results to form single waveform. This method could retain response from higher harmonics of certain signal compared to conventional single-frequency simulation. Problems of parasitic element that is hard to modeled as lumped component could also be addressed. A 2.2 kW e-Scooter power train inverter is implemented to verify the applicability of proposed methodology.