A 55nm, 0.6mm2 Bluetooth SoC integrated in cellular baseband chip with enhanced coexistence

2013 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2013-12-23 DOI:10.1109/ASSCC.2013.6691015

Y. Shih, Hong-Lin Chu, Wei-Kai Hong, Chao-Ching Hung, A. Tanzil, Y. Huang, Jun-Yu Chen, Li-Han Hung, Lan-chou Cho, Junmin Cao, Yen-Chuan Huang, Y. Hsueh, Y. Chung

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引用次数: 10

Abstract

This paper describes a 55nm, 0.6mm2 Bluetooth SoC integrated in cellular baseband. Several techniques are used to enhance co-existence performance of Bluetooth with cellular and Wi-Fi. First is the design of current-mode interfaces from LNA to complex BPF for better linearity and the additional antialiasing LPF placed before ADC for outband rejection in the RX. Second is the use of a passive voltage sampling mixer to lower out-of-band emission noise floor in TX. Moreover, only two inductors are used, one of which is a field-cancelling inductor used in VCO layout to achieve a spur-free LO signal, minimizing magnetic coupling from other parts of SoC. The TX output power is +11dBm at BDR mode and +8dBm at EDR3 mode, with 1.5-kHz frequency drift and <;6% RMS DEVM. The RX sensitivity is better than -96.5dBm and -89.2dBm for BDR and EDR3 modes respectively. The measured BT RX sensitivity is -57dBm at BDR mode while co-existing with -5dBm of Wi-Fi 54Mbps OFDM.

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55nm, 0.6mm2蓝牙SoC集成在蜂窝基带芯片，增强共存

本文介绍了一种集成在蜂窝基带中的55nm、0.6mm2蓝牙SoC。为了提高蓝牙与蜂窝和Wi-Fi的共存性能，采用了几种技术。首先是设计从LNA到复杂BPF的电流模式接口，以获得更好的线性度，并在ADC之前放置额外的抗混叠LPF，用于RX中的带外抑制。其次是使用无源电压采样混频器来降低TX的带外发射噪声底。此外，仅使用两个电感，其中一个是用于VCO布局的场抵消电感，以实现无杂散的LO信号，最大限度地减少SoC其他部分的磁耦合。TX输出功率在BDR模式下为+11dBm，在EDR3模式下为+8dBm，频率漂移为1.5 khz, RMS DEVM < 6%。在BDR和EDR3模式下，RX灵敏度分别优于-96.5dBm和-89.2dBm。测量的BT RX灵敏度在BDR模式下为-57dBm，同时与Wi-Fi 54Mbps OFDM共存-5dBm。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)

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