A model for a universally testable logic element

Abstract

A model is presented for a logic element to be used in the design of testable logic circuits. The logic element consists of a threshold gate and an exclusive-or. A circuit designed exclusively with such an element, according to the rules set here, can be tested for all data stuck-at faults. Only two predetermined test vectors are needed for testing any combinational circuit and four for any sequential circuit, for data stuck-at faults, regardless of the complexity of the circuit. A possible CMOS circuit realization for the model is given.