Industry-track: Towards Agile Design of Neural Processing Unit

Binyi Wu, W. Furtner, Bernd Waschneck, C. Mayr
{"title":"Industry-track: Towards Agile Design of Neural Processing Unit","authors":"Binyi Wu, W. Furtner, Bernd Waschneck, C. Mayr","doi":"10.1109/CODES-ISSS55005.2022.00015","DOIUrl":null,"url":null,"abstract":"More and more specialized processors, known as Neural Processing Units (NPUs), have been or are being built for deep neural network inference. Design and optimization of this kind of processor are inseparable from the deep learning ecosystem and corresponding underlying software. This HW/SW co-design requirement poses challenges for designers. Therefore, in this work, we experiment with an agile development method to shorten the development cycles of NPUs. We utilize Chisel for hardware design and develop a custom Chisel backend for generating cycle-accurate simulators with C++/Python APIs. On top of the simulator, we built a Python software stack for software development, performance evaluation, and simulation-based verification. The proposed method is purely software and does not involve real hardware, thus allowing the integration of software agile development methods into digital designs. In the experiments, we show how it helps us identify inherent hardware limitations and how it shortens our development cycles.","PeriodicalId":129167,"journal":{"name":"2022 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CODES-ISSS55005.2022.00015","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

Abstract

More and more specialized processors, known as Neural Processing Units (NPUs), have been or are being built for deep neural network inference. Design and optimization of this kind of processor are inseparable from the deep learning ecosystem and corresponding underlying software. This HW/SW co-design requirement poses challenges for designers. Therefore, in this work, we experiment with an agile development method to shorten the development cycles of NPUs. We utilize Chisel for hardware design and develop a custom Chisel backend for generating cycle-accurate simulators with C++/Python APIs. On top of the simulator, we built a Python software stack for software development, performance evaluation, and simulation-based verification. The proposed method is purely software and does not involve real hardware, thus allowing the integration of software agile development methods into digital designs. In the experiments, we show how it helps us identify inherent hardware limitations and how it shortens our development cycles.
行业动态:神经处理单元的敏捷设计
越来越多的专用处理器,被称为神经处理单元(npu),已经或正在为深度神经网络推理而建造。这种处理器的设计和优化离不开深度学习生态系统和相应的底层软件。这种硬件/软件协同设计要求给设计师带来了挑战。因此,在这项工作中,我们尝试使用敏捷开发方法来缩短npu的开发周期。我们利用Chisel进行硬件设计,并开发了一个自定义的Chisel后端,用于使用c++ /Python api生成周期精确的模拟器。在模拟器之上,我们构建了一个Python软件栈,用于软件开发、性能评估和基于仿真的验证。所提出的方法是纯软件的,不涉及实际的硬件,从而允许将软件敏捷开发方法集成到数字设计中。在实验中,我们展示了它如何帮助我们识别固有的硬件限制,以及它如何缩短我们的开发周期。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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